Responsibilities

• Work at various levels of implementation of hierarchical chip (Blocks and Top)
• Floor plan and partition, power plan, bump plan
• Integration of different sub-blocks and custom macros/IPs
• Physical implementation of blocks
• Blocks and top-level timing IR analysis and closure
• Physical Verification
• Develop, support and maintain physical design flows and methodologies

Requirements

• B.Tech / M.Tech from a reputed university with 8-12+ years of experience.
• Good knowledge of VLSI process and device characteristics.
• Experience doing physical design targeted to the 7nm/16nm FinFet process.
• Good knowledge of cell libraries various views and models.
• Good understanding of static timing analysis (STA), EM/IR and sign-off.
• Strong hands-on experience with: Chip Level / Sub-chip level floor planning, partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification – block and chip level.
• EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC etc.
• Good software and scripting skills (Python, tcl).
• Good communication skills and the ability and desire to work as part of a team.
• Self-driven individual and an excellent team player.
• Good communication abilities.

Responsibilities

• Working with the software design team to implement new features.
• Own development of applications and adoption of new technology packages.
• Improve performance, accuracy and throughput of product application.
• Benchmark and qualify developed software to ensure product quality is maintained in each feature implementation.

Requirements

• BTech/MTech/PhD in Computer Science or Electrical Engineering from a reputed university.
• 10+ years of CAD/Software development experience.
• Strong organizational and project planning skills.
• Strong knowledge is various tools from major leading industry EDA leaders such as Cadence, Mentor and Synopsys.
• Proficiency with languages such as Python, tcl, and shell scripting.
• Specific knowledge in PnR tools and VLSI design workflows.
• Strong problem-solving and communication skills, with attention to detail.

Responsibilities

• Block level and chip level timing analysis.
• Timing analysis of different kinds of interfaces at chip level.
• Work with the design and implementation teams to develop and qualify timing constraints.
• Work on methodology development for timing analysis and timing closure.
• Contribute to the STA flow development.
• Work closely with the physical design engineers to resolve implementation related timing issues.
• Create methodologies for customized timing checks for different IPs, interfaces etc.
• Validation of library timing data (qualification of libraries).

Requirements

• BTech/MTech from a reputed university.
• 8-12 years of hands-on experience in timing analysis.
• Experience in doing SoC level timing analysis.
• Should be familiar with timing analysis for hierarchical designs.
• Familiarity with different types of interfaces like PCIe, SATA, USB, DDR etc.
• Worked on technology nodes 16nm and 7nm.
• Proficiency in industry standard STA tools (Tempus and PrimeTime).
• Good scripting skill in Tcl and Python.
• Familiarity with different physical design tools preferably Cadence Innovus.

Responsibilities

• Implementing DFT architecture features in the design.
• SCAN insertion, scan DRC analysis and debug.
• Achieving high SCAN coverage and low DPPM.
• ATPG vector generation and ATE BringUp.
• JTAG implementation and verification.
• MBIST and JTAG implementation and verification.
• IP-SOC integration methodology and Implementation of DFT structures to support IP test requirements.
• Contributions to overall DFT flow / automation.
• Contributions to SCAN, MBIST and JTAG timing constraints/analysis.
• Simulation and Verification of DFT structures in the design

Requirements

• BTech/MTech preferred.
• Strong understanding of DFT methodologies and experience in standard DFT tools.
• Experience on SoCs with multiple scan chains and clocks.
• Hands On experience in SCAN/MBIST/JTAG implementation at chip & block level.
• Knowledge on DFT simulations and debugging.
• Knowledge on Test mode timing constraint development and analysis is a plus.
• Understanding of test compression and ATE debug is a plus.
• Having strong scripting abilities is a plus.

Requirements

• B.Tech / M.Tech in Electronics/VLSI from a reputed university.
• Basic understanding of device electronics, digital design, logic synthesis, timing analysis, physical design, scripting/programming languages (Python, Tcl) etc.
• Familiarity with any of the industry standard EDA tools from Cadence/Synopsys/Mentor for physical design/DFT/STA is a plus.
• Willingness to learn and work in a dynamic start-up environment.
• Good communication abilities both written and oral.
• Work as part of a team, be a good team player.

Responsibilities

• Develop, support and maintain physical design flows and methodologies.
• As part of the physical design team you will be working on cutting edge designs in 7nm and 16nm process nodes.

Requirements

• BTech / MTech from a reputed University with 2-7 years work experience.
• Good knowledge of executing designs from RTL to GDSII.
• Experience working on lower process nodes (16nm and below – FinFets).
• Good understanding of STA, EM/IR and sign-off physical verification flows.
• Good knowledge of EDA tools from Cadence Mentor and Synopsys is required. In particular experience with Innovus, Tempus/PT-SI, Calibre, StarXT/Quantus, and Conformal LEC is essential.
• Strong hands-on experience with: Synthesis, floor planning, place & route using industry standard tools, Timing and IR analysis and closure, Physical design verification, Formal verification.
• Good software and scripting skills (python, tcl, perl)
• Self-driven individual and an excellent team player
• Good communication abilities

Responsibilities

• Block level and chip level timing analysis.
• Timing analysis of different kinds of interfaces at chip level.
• Work with the design and implementation teams to develop and qualify timing constraints.
• Work closely with the physical design engineers to resolve implementation related timing issues.
• Validation of library timing data (qualification of libraries).

Requirements

• BTech/MTech from a reputed university.
• 2-4 years of hands-on experience in timing analysis.
• Experience in doing SoC level timing analysis.
• Should be familiar with timing analysis for hierarchical designs.
• Familiarity with different types of interfaces like PCIe, SATA, USB, DDR etc.
• Worked on technology nodes 16nm and 7nm.
• Proficiency in industry standard STA tools (Tempus and PrimeTime).
• Good scripting skill in Tcl and Python.
• Familiarity with different physical design tools preferably Cadence Innovus.

Responsibilities

• SCAN insertion, scan DRC analysis and debug.
• ATPG vector generation and ATE debug.
• MBIST and JTAG implementation and verification.
• Overall DFT flow / automation.
• SCAN, MBIST and JTAG timing constraints/analysis.
• Simulation and Verification of DFT structures in the design.

Requirements

• BTech/MTech preferred.
• Strong understanding of DFT methodologies and experience in standard DFT tools.
• Hands On experience in SCAN/MBIST/JTAG implementation at physical block level.
• Experience on DFT Simulations setup and debug.
• Test mode timing constraint development and analysis is a plus.
• Understanding of test compression and ATE debug is a plus.

Responsibilities

• Stay on top of project plans, including project scope, objectives, release schedule, milestones, deliverables, and commitments involving all relevant stakeholders and ensuring technical feasibility.
• Follow up on project activities and solve technical and non-technical challenges to keep the projects on schedule.
• Coordinate calls, meetings and daily communications between customers and our business and technical teams throughout the project life cycle.
• Timely escalation of key matters to the management team.
• Develop processes and methodologies for improving customer project execution.

Requirements

Minimum Qualifications

• Bachelor’s degree in Computer Science or Electrical Engineering or equivalent technical field with 5+ years of relevant experience.
• 3+ years of customer facing or technical project/program management experience.
• 3+ years leadership experience, including driving cross-functional activities.
• 5+ years of experience working in one or more of the following technical fields: IC hardware design, IC hardware validation, EDA software development, EDA software integration and QA, debug.

Preferred Qualifications

• Preferred Qualifications
• MS in Computer Science or Electrical Engineering, or equivalent technical field.
• Experience with advanced semiconductor process nodes.
• Experience with medium to large scale IC development projects.
• Experience with medium to large scale software development products.
• Experience leading large-scale change and transition management.

Additional Skills

• Demonstrated effectiveness in bringing teams together to focus on meeting goals.
• Effective oral and written communication skills.
• Work with different teams and team dynamics through various stages of problem solving.
• Synthesize complex information into clear messages to the organization and management.
• Act quickly and decisively to bring clarity to the project team in ambiguous situations.

Responsibilities

For existing customers, you will need to understand the customer’s usage of the application, answer any usage related questions, improve and expand on their methodologies with developing features so the customer can take full advantage of an application. For new customers, conduct technical presentations, training and product demonstrations. Take best practices and learnings from evaluations and customer interactions, and have regular communication with the product development team so improvements can be integrated into the product.

• Understand our software’s application interface by collaborating with enterprise and application architects
• Understand the unix/linux environment and application dependencies
• Understand customer applications and develop usage models based on our applications
• Lead customer education for new features and how specific usage models can benefit from them

Qualifications:

• MTech / PhD in IT or Computer Science from a reputed university
• 5+ years experience in VLSI and EDA
• Experience using Digital software with at least one major EDA vendor
• Working knowledge of Python / Perl / TCL scripting languages for automation
• Working Knowledge of unix/linux engineering environment
• Knowledge of sql databases or aws database services a plus

Industry

Computer Software
Computer Hardware
Semiconductor