Interchip solutions
A revolutionary way of delivering interconnect solutions to accelerate heterogeneous integration of multiple die in chiplet based systems.
Solution Optimized For Your Application
Apex is developing an automated, scalable, high-bandwidth, low-latency, low-power, standard or custom based, die-to-die PHY compiler that can deliver a PHY + interconnect solution optimized for your system and application
Chiplet Systems
Our solution focuses on two major types of chiplet systems
Organic substrate-based
Silicon interposer-based: InFO_os and CoWos
Optimized for Your Needs
Support for multiple technology nodes
Compiled PHY and interconnect routing optimized for substrate type