AI Solutions
Apex Semiconductor is developing innovative AI solutions to streamline the chip design process and significantly reduce production time. Our solutions include timing estimation, on-die power distribution, on-die clock distribution, and design rule fixes.
Cross-PVT Timing Estimation
Apex’s AI Timing Estimator (TE) makes all-corner timing analysis possible for all phases of the design, starting as early as completion of physical synthesis. Our paradigm-changing solution quickly and accurately reports design timing paths across all operating conditions, enabling designers to optimize their design much earlier in the design cycle.
Key benefits include:
- • Exhaustively evaluates millions of timing paths across operating conditions at multitude orders of magnitude faster than traditional analysis methods
- • Enables tight integration between logic optimization and physical design effects
- • Captures non-linear circuit effects in design corners to accurately reflect timing across wide range of operating conditions
- • Mitigates the need for multiple tape-outs due to sub-optimal performance across product operation space
Coming Soon
Power Supply Inference Compiler
Apex’s AI-powered power supply inference compiler is an innovative solution for on-die power distribution. The tool integrates decades of power distribution expertise with on-die voltage drop and timing hotspots to produce an optimized power distribution design. As the height of the stack-up increases with each process technology advancement, the inference compiler uniquely balances available design resources against design hotspots to achieve a locally targeted solution that is highly design specific.
Clock Distribution Compiler
Apex’s AI-powered clock distribution inference compiler is an innovative solution for on-die clock distribution. With increasing design and clock complexity, low-skew clock networks are critical to high performance. Apex’s clock compiler solution integrates design hotspot knowledge with proven high-performance techniques like high-density clock meshes and automated techniques like low-density meshes and tree synthesis. This solution can quickly achieve a low-skew, low-power clock network that is highly design specific.
Automated Design Rule Fixes
Apex’s design rule fixing utility is a highly process-specific solution that targets commonly observed design rule violations. With a series of proven, low-impact solutions for all common design rule violations and an automated application nature, this product bridges the gap between implementation, integration, physical verification, and tapeout. The design rule fixing utility focuses on minimizing manual effort, leading to a considerable reduction in design iterations and expediting the design schedule.