One of the most crucial and challenging aspects of VLSI design is timing closure, which ensures that a circuit can operate at its intended frequency and meet power, performance, and area specifications. After designing the chip, designers must validate the speed that it runs, the speed at which it interacts with other chips, and other timing interactions that affect performance.

To test these timing interactions, designers use timing analysis to measure the delay of the design at various stages and make subsequent design fixes. As VLSI designs become increasingly complex and the number of timing paths and operating conditions has grown, however, modern timing analysis methods have developed runtime, coverage, and accuracy issues.

This paper describes Apex’s proprietary AI-based Timing Estimator methodology.

Download

As the first step in VLSI design, design exploration is a leading indicator of overall design performance and time to market. The primary objectives of this stage are designing and verifying the register-transfer level (RTL) and enabling the physical implementation of the chip. Because the RTL serves as the blueprint of the integrated circuit, the design exploration phase is essential to ensuring that the chip will meet product specifications.

As chips become more complex, however, this design phase has become increasingly challenging and time-consuming. The modern methodology depends heavily on physical design engineers to execute a manual, iterative, and resource-intensive process that can take over six months to complete.

This paper describes Apex’s innovative method of performing design exploration in a quick, robust, and automated fashion.

Download

The complexity of modern VLSI design flows requires grid computing, in which a large group of networked computers works together to perform tasks simultaneously. A typical design flow can involve hundreds or even thousands of these tasks, also known as “jobs,” running at the same time. VLSI companies use job scheduler software to enable individual users to manage large numbers of jobs throughout the design process.

Well-known examples of job scheduler software include IBM Spectrum LSFTM, Univa Grid EngineTM, and the open-source SLURMTM project — all of which only provide a limited feature set for strategic job management. While job scheduler applications offer an interface for launching jobs, they lack the capability to intelligently manage, track, and analyze the thousands of jobs and results in the design flow.

Download