Design For Test (DFT) Services
Apex’s DFT solution is a cutting-edge and cost-effective service optimized for your design.
Our DFT service provides a comprehensive methodology for inserting test structures into a design and integrating existing test structures embedded in IP. We automate test structure insertion and design analysis, minimizing the number of required modifications or perturbations to the front-end design. The Apex DFT flow is completely integrated with all other parts of the Apollo design flow and provides a cohesive test solution that delivers high coverage.
Industry-Standard Feature Support
- IEEE 1687 IJTAG support
- 1149.1 / 1149.6 boundary scan
- Memory BIST and repair
- Scan stitching
- Scan compression
- Core wrapper insertion
- On-chip clock controller insertion
- Test point insertion
- IP test wrapper insertion
- EFUSE insertion
- Pattern generation
- Pattern simulation
Advanced Feature Support
- MBIST wrappers and logic insertion to either RTL or netlist
- Insertion of clock conditioning and control to ensure design stability
- Integration of post-scan netlists as well as IPs with embedded subchains
- Conditioning and isolation of analog IP
- Synthesis of inserted logic with automated SDC generation
- Automated logical equivalence checking
- Automated DRC checks and repair
- Multi-pass test pattern generation to analyze coverage
- Diagnosis for yield analysis and improvement
- Consolidated reports that reduce iterations and estimation of tester requirements
- Intelligent test point insertion to reduce overhead for area and timing closure
- Latch-based design support with minimal logic insertion
- Design simulation in all DFT modes